A delay lock loop (“DLL”) is an electronic circuit that takes an input signal and outputs a plurality of phase delayed signals each having the same frequency as the input signal but each being phased delayed by some amount. The phase delayed signals may have any configured phase delay, but typically have evenly spaced phase delays ranging between 0° and 360°. DLLs may be used in a variety of circuits, such as communication circuits and input/output (“I/O”) circuitry (e.g., receiver and driver circuitry). For example, DLLs may be used in receiver circuitry for adjusting the sampling phase of the receiver.
A phase lock loop (“PLL”) is an electronic circuit which typically includes a voltage controlled or current controlled oscillator that is constantly adjusted to match the frequency (and thus lock on) of an input clock signal. PLLs are also commonly used in communication circuit and I/O circuitry to implement a variety of functions. For example, PLLs are used to generate clock signals, to extract clock signals from an incoming data streams, to modulate and demodulate signals, to reconstitute signals with less noise, to multiple or divide frequencies, or otherwise.
When initially turned on, conventional DLLs and PLLs require a certain minimum amount of time to stabilize and acquire a feedback lock on the input signal. During this transient startup phase, the output(s) of the DLL or PLL are unreliable. The typical transient startup time of conventional DLLs and PLLs can last for ≈100 ns and ≈1 ms, respectively, until the feedback loop stabilizes, thereby “acquiring lock”, and entering its steady state of operation during which the output may be reliably used to drive downstream circuitry.
Waiting for expiration of the ≈100 ns transient startup time is a significant period of time in relation to modern high speed gigahertz circuits. Accordingly, when circuits including DLLs or PLLs are placed in low power sleep states, the DLLs and PLLs are often left operating—consuming power—so as to avoid cycling through the costly transient startup phase upon exiting the sleep state.